DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 135

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

6.2
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Flash memory power control register (FLPWCR)
• Flash memory enable register (FENR)
6.2.1
FLMCR1 is a register that makes the flash memory enter the programming mode, programming-
verifying mode, erasing mode, or erasing-verifying mode. For details on register setting, refer to
section 6.4, Flash Memory Programming/Erasure.
Bit
7
6
5
4
Bit Name

SWE
ESU
PSU
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
Initial
Value
0
0
0
0
R/W

R/W
R/W
R/W
Description
Reserved
This bit is always read as 0.
Software Write Enable
When this bit is set to 1, flash memory
programming/erasure is enabled. When this bit is cleared
to 0, other FLMCR1 register bits and all EBR1 bits cannot
be set.
Erase Setup
When this bit is set to 1, the flash memory enters to the
erasure setup state. When it is cleared to 0, the erasure
setup state is released. Set this bit to 1 before setting the
E bit in FLMCR1 to 1.
Program Setup
When this bit is set to 1, the flash memory enters to the
programming setup state. When it is cleared to 0, the
programming setup state is released. Set this bit to 1
before setting the P bit in FLMCR1 to 1.
Rev. 3.00 May 15, 2007 Page 101 of 518
REJ09B0152-0300
Section 6 ROM