DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 401

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

To set the interrupt, follow the procedure shown in figure 18.3 or 18.4.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Set the CME bit. Wait a conversion time for the comparator stabilized.
Read the CDR bit.
Set the CMIE bit.
Read the CDR bit. At this time, the CDR bit is latched in the internal latch for the comparator
and the internal interrupt enable signal is asserted.
As the relationship between the voltage on the COMP pin and reference voltage is changed,
a difference occurs between the output level of the internal latch and the CDR bit. Then an
interrupt is generated.
Clear the CMF bit in the interrupt handler. When reading the CMF bit for clearing it, the CDR bit is
also read since those bits are in the same register. Therefore, the output of the internal latch is
updated. Go to step [5] to continue use of the interrupt.
Clear the CMIE bit to clear the interrupt setting and clear the CME bit to stop the comparator.
Clearing the CMIE bit negates the internal interrupt enable signal.
The interrupt flag may be set depending on the internal states of the comparator, pin states, the
timing of setting the internal interrupt enable signal shown in step [4], and the timing of the CDR bit
latched. To avoid this, execute steps [2] to [4] continuously or ensure that the CMF bit is cleared
using the I bit in CCR as shown in figure 18.4.
When CMR = 0 and CMRS3 to CMRS0 = B'1000 (VIH = 19/30 Vcc)
CDR (CMLS = 0)
CME
CMIE
Interrupt enable signal
CDR read signal
Internal latch
for comparator
CMF
19/30 Vcc
Stabilization time
(conversion time)
Figure 18.3 Procedure for Setting Interrupt (1)
Conversion time
Unstable
[2]
[1]
[3]
[4]
[4]
[5]
[6]
[6]
[6]
Rev. 3.00 May 15, 2007 Page 367 of 518
[5]
Conversion time
[6]
[6]
[6]
Section 18 Comparators
[7]
[7]
Voltage on
REJ09B0152-0300
COMP pin