DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 277

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

14.3.8
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF.
Tables 14.2 and 14.3 show the relationship between the N setting in BRR and the n setting in bits
CKS1 and CKS0 in SMR in asynchronous mode. Table 14.5 shows the maximum bit rate for each
frequency in asynchronous mode. The values shown in these tables are values in active (high-
speed) mode. When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit
rate in table 14.5 is doubled. Table 14.6 shows the relationship between the N setting in BRR and
the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in
table 14.6 are values in active (high-speed) mode. The N setting in BRR and error for other
operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode and ABCS Bit is 0]
[Asynchronous Mode and ABCS Bit is 1]
[Legend]
B:
N:
φ:
n:
N =
Error (%) =
N =
Error (%) =
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 14.4)
32 × 2
16 × 2
Bit Rate Register (BRR)
φ
φ
2n
2n
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.2)
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.3)
× B
× B
– 1
– 1
R (bit rate in left-hand column in table 14.2)
R (bit rate in left-hand column in table 14.3)
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Rev. 3.00 May 15, 2007 Page 243 of 518
REJ09B0152-0300
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