DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 295

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

14.4.4
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
• Parity check
• Stop bit check
• Status check
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or
even) set in bit PM in the serial mode register (SMR).
The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred
from RSR to RDR.
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI3 interrupt request is generated. Receive data is not transferred to RDR.
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated. Continuous reception is possible because the RXI3 interrupt routine reads the
receive data transferred to RDR before reception of the next receive data has been completed.
Serial Data Reception
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Rev. 3.00 May 15, 2007 Page 261 of 518
REJ09B0152-0300