DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 215

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

10.6
Table 10.3 shows the timer W operating modes.
Table 10.3 Timer W Operating Modes
[Legend]
10.7
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
3. Depending on the timing, TCNT may be incremented by a switch between different internal
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
Clock
Source
FTCI
φw, φw/4,
φw/16
φ, φ/2, φ/4,
φ/8
system clock cycles; shorter pulses will not be detected correctly. The system clock described
here indicates the clock set for the CPU operation. For example, in the φw/8 operation, at least
φw x 16 clock cycles are required as the pulse width.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 10.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is, the divided system clock (φ). Therefore, as
shown in figure 10.25 the switch is from a low clock signal to a high clock signal, the
switchover is seen as a rising edge, causing TCNT to increment.
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
High-
speed
ο
ο
ο
Timer W Operating Modes
Usage Notes
ο: Counting enabled
×: Counting disabled (Counter value retained)
Active
Medium-
speed
ο
ο
ο
High-
speed
ο
ο
ο
Sleep
Medium-
speed
ο
ο
ο
Watch
×
×
×
Sub-
active
ο
ο
×
Sub-
sleep
ο
ο
×
Standby
×
×
×
Rev. 3.00 May 15, 2007 Page 181 of 518
Standby to
Active
×
×
×
Oscillation Stabilization Time
Subsleep to
Active
×
×
×
Section 10 Timer W
REJ09B0152-0300
Watch to
Active
×
×
×