DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 539

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Item
Table 12.2 The Value of "xx"
Section 13 Asynchronous Event
Counter (AEC)
13.3.6 Event Counter H (ECH)
13.3.7 Event Counter L (ECL)
Section 14 Serial Communication
Interface 3 (SCI3, IrDA)
14.3.5 Serial Mode Register
(SMR)
Page Revisions (See Manual for Details)
211
222
222
231
235
Added
The serial communication interface 3 (SCI3) can handle
both asynchronous and clock synchronous serial
communication. In the asynchronous method, serial
data communication can be carried out using standard
asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an
Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial
Modified
Modified
Deleted
communication between processors (multiprocessor
communication function).
Modified
Bit
2
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name Description
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Bit Name Description
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Bit Name Description
MP
Either the external asynchronous event AEVH pin,
φ/2, φ/4, or φ/8, or the overflow signal from lower 8-
bit counter ECL can be selected as the input clock
source. ECH can be cleared to H'00 when the
CRCH bit in ECCSR is cleared to 0.
Either the external asynchronous event AEVL pin,
φ/2, φ/4, or φ/8 can be selected as the input clock
source. ECL can be cleared to H'00 when the
CRCL bit in ECCSR is cleared to 0.
5-Bit CommunicationWhen this bit is set to 1, the
5-bit communication format is enabled. Make sure
to set bit 5 (PF) to 1 when setting this bit (MP) to 1.
Rev. 3.00 May 15, 2007 Page 505 of 516
REJ09B0152-0300