DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 95

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

3.8.5
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC.
When an interrupt request is generated, an interrupt is requested to the CPU. At that time, if the
CPU is executing an instruction that disables interrupts, the CPU always executes the next
instruction after the instruction execution is completed.
3.8.6
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is
not accepted until the transfer is completed.
With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during
transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is
issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction.
Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
3.8.7
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt
flag register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is
executed while the I bit is 0 and conflict between the instruction execution and the interrupt
request generation occurs, exception handling, which corresponds to the interrupt request
generated after instruction execution of the above operation is completed, is executed.
L1: EEPMOV.W
Instructions that Disable Interrupts
Interrupts during Execution of EEPMOV Instruction
IENR Clearing
MOV.W
BNE
R4,R4
L1
Rev. 3.00 May 15, 2007 Page 61 of 516
Section 3 Exception Handling
REJ09B0152-0300