DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 139

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

6.3.1
Table 6.2 shows the boot mode operations between a reset released and a branch to the
programming control program.
This LSI includes a system clock oscillator which is operated by a resonator or an external clock
and on-chip oscillator.
In Boot Mode, since the system clock oscillator is selected, connect a resonator to OSC1 and
OSC2, or an external clock signal to OSC1.
1. When the boot mode is used, the flash memory programming control program must be
2. SCI3 is set to the asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit,
3. When the boot program is initiated, this LSI measures the low-level period of serial
4. After matching the bit rates, SCI3 transmits one byte of H'00 to the host to indicate the
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The programming
prepared in the host beforehand. Prepare a programming control program in accordance with
the description in section 6.4, Flash Memory Programming/Erasure.
and no parity. The inversion function of the TXD and RXD pins by SPCR is set to “Not to be
inverted,” so do not put inverters between the host and this LSI.
communication data (H'00) continuously transmitted in asynchronous mode from the host.
This LSI then calculates the bit rate of the transfer from the host, and adjusts the SCI3 bit rate
to match that of the host. The reset signal should be negated while the RXD pin is driven high.
The RXD and TXD pins should be pulled up on the board if necessary. After the reset signal is
negated, it takes approximately 100 states before this LSI is ready to measure the low-level
period.
completion of bit rate adjustment. The host should confirm that it has received this adjustment
end code (H'00) normally and then transmit one byte of H'55 to this LSI. If reception could not
be performed normally, initiate the boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 6.3.
control program transmitted from the host can be stored in the area from H'FB80 to H'FF7F.
The boot program area cannot be used until control of the execution is switched from the boot
program to the programming control program.
Boot Mode
Rev. 3.00 May 15, 2007 Page 105 of 518
REJ09B0152-0300
Section 6 ROM