DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 128

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
Section 5 Power-Down Modes
5.3.6
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in
SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode
after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (6).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
Rev. 3.00 May 15, 2007 Page 94 of 516
REJ09B0152-0300
Example:
Direct transition time = (2 + 1) × 8tw + 8192 × 1tosc + 14 × 8tosc = 24tw + 8304tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
When φw/8 and φosc/8 are selected as the CPU operating clock before and after
the transition, respectively, and wait time = 8192 states
processing states)} × (tsubcyc before transition) + (Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states) × (tcyc after transition)……………………….………………..(6)

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