DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 259

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

13.4.3
When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when
IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and
so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from
outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIEGS1
and AIEGS0 in AEGSR.
13.4.4
When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically by controlling event counter PWM. In this case, ECH and ECL cannot be
controlled individually.
IECPWM can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIEGS1 and AIEGS0 in AEGSR.
IRQAEC Operation
Event Counter PWM Operation
Section 13 Asynchronous Event Counter (AEC)
Rev. 3.00 May 15, 2007 Page 225 of 516
REJ09B0152-0300