M30624FGNGP#D5 Renesas Electronics America, M30624FGNGP#D5 Datasheet - Page 155

• Manufacturer Part Number: M30624FGNGP#D5
• Description: IC M16C MCU FLASH 256K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGNGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

A-D Converter
152
A-D Converter
Table 1.18.1. Performance of A-D converter
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide the f
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10
registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address
03D7
when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from V
ing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D7
connect V
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.18.1 shows the performance of the A-D converter. Figure 1.18.1 shows the block diagram of the
A-D converter, and Figures 1.18.2 and 1.18.3 show the A-D converter-related registers.
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AV
Operating clock
Resolution
Absolute precision
Operating modes
Analog input pins
A-D conversion start condition • Software trigger
Conversion speed per pin • Without sample and hold function
16
divide the f
Without sample and hold function, set the
With the sample and hold function, set the
) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (V
REF
Item
.
AD
AD
0
AD
(Note 2) V
to P10
if V
if f(X
CC
7
IN
, P9
is less than 3.0V, and make
) exceeds 10MH
8-bit or 10-bit (selectable)
V
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8pins (AN
• External trigger (can be retriggered)
• With sample and hold function
A-D conversion starts when the A-D conversion start flag changes to “1”
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
AD
8-bit resolution: 49
8-bit resolution: 28
CC
CC
5
, P9
TRG
= 3.3V f
= 3.3V • Without sample and hold function
6
/P9
and P0
CC
0
to AN
7
(V
• With sample and hold function (8-bit resolution)
• With sample and hold function (10-bit resolution)
input changes from “H” to “L”
AD
CC
0
Z
AN
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : 7LSB
AN
/divide-by-2 of f
, and make
to P0
)
5LSB
2LSB
7
) + 2pins (ANEX0 and ANEX1) + 8pins (AN
0
00
to AN
AD
AD
to AN
7
AD
AD
also function as the analog signal input pins. The direction
cycles, 10-bit resolution: 59
cycles, 10-bit resolution: 33
frequency to 250kH
frequency to 1MH
7
07
AD
input : 5LSB
AD
input : 7LSB
frequency equal to or lower than f
AD
Performance
frequency equal to or less than 10MHz. And
/divide-by-4 of f
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Z
Z
min.
min.
AD
, f
AD
AD
AD
M16C / 62N Group
=f(X
cycles
cycles
Mitsubishi microcomputers
IN
00
)
AD
to AN
/2.
REF
07
, reduc-
)
16
REF
to
)