M30624FGNGP#D5 Renesas Electronics America, M30624FGNGP#D5 Datasheet - Page 186

• Manufacturer Part Number: M30624FGNGP#D5
• Description: IC M16C MCU FLASH 256K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGNGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Electrical characteristics
Note 3: Specify a product of -40°C to 85°C to use it.
Switching characteristics (referenced to V
85
Table 1.26.21. Memory expansion and microprocessor modes (with no wait)
Note 2: This is standard value shows the timing when the output is off,
Figure 1.26.1. Port P0 to P10 measurement circuit
Note 1: Calculated according to the BCLK frequency as follows:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
h(RD-AD)
d(BCLK-AD)
h(BCLK-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
Symbol
o
C (Note 3), CM15 = “1” unless otherwise specified)
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output “L” level is
td(DB – WR) =
Address output delay time
Address output hold time (RD standard)
Address output hold time (WR standard)
WR signal output hold time
Data output hold time (BCLK standard)
Address output hold time (BCLK standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
Data output delay time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
t = –CR X ln (1 – V
t = – 30pF X 1k X ln (1 – 0.2V
= 6.7ns.
f(BCLK) X 2
10
OL
Parameter
9
= 0.2V
OL
– 50
/ V
CC
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
CC
, C = 30pF, R = 1k , hold time
[ns]
)
CC
CC
= 3.3V, V
/ V
CC
30pF
)
Measuring condition
Figure 1.26.1
SS
= 0V at Topr = – 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
Min.
–4
Standard
0
0
4
4
0
0
4
0
o
DBi
Max.
C to 85
50
50
40
40
40
50
M16C / 62N Group
Mitsubishi microcomputers
o
Unit
C / – 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
R
o
C to
183