HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 106

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

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CPU Data Access Bus Cycle:
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DMA Cycle:
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Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054
Conditions set: Address = H'00030147, Bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
No user break interrupt occurs, because instructions are always fetched from even addresses. If
the first fetched address after a branch is odd and a user break is set on this address, however,
user break exception processing will be carried out after address error exception processing.
Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A
Conditions set: Address = H'00123456, Bus cycle = CPU, data access, write, word
A user break interrupt occurs when word data is written to address H'00123456.
Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066
Conditions set: Address = H'00A80391, Bus cycle = CPU, data access, read, word
No user break interrupt occurs, because word data access is always to an even address.
Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7
Conditions set: Address = H'0076BCDC, Bus cycle = DMA, data access, read, long word
A user break interrupt occurs when long word data is read from address H'0076BCDC.
Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094
Conditions set: Address = H'002345C8, Bus cycle = DMA, instruction fetch, read (operand
size not included)
No user break interrupt occurs, because a DMA cycle includes no instruction fetch.
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