HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 259

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Note: Undefined
•
•
Bit 2: OVIE
0
•
Bit 1: IMIEB
0
1
•
Bit 0: IMIEA
0
1
10.3
10.3.1
The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B
(BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a
16-bit data bus. Byte access is also possible. Read and write operations performed on the TCNT in
word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and
TCNTL are shown in figures 10.8–10.11.
Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Bit 2 (overflow interrupt enable (OVIE)): When the TSR overflow flag (OVF) is set to 1,
OVIE enables or disables interrupt requests from the OVF.
Bit 1 (input capture/compare match interrupt enable B (IMIEB)): When the IMFB bit of the
TSR is set to 1, IMIEB enables or disables the interrupt requests from the IMFB.
Bit 0 (input capture/compare match interrupt enable A (IMIEA)): When the IMFA bit of the
TSR is set to 1, IMIEA enables or disables the interrupt requests from the IMFA.
1
Initial value:
Bit name:
CPU Interface
16-Bit Accessible Registers
R/W:
Bit:
—
—
7
*
Description
Disables interrupt requests by the IMFA (IMIA) (initial value)
Enables interrupt requests from the IMFA (IMIA)
Description
Disables interrupt requests by the OVF (initial value)
Enables interrupt requests from the OVF
Description
Disables interrupt requests by the IMFB (IMIB) (initial value)
Enables interrupt requests from the IMFB (IMIB)
—
—
6
1
—
—
5
1
—
—
4
1
—
—
3
1
OVIE
R/W
2
0
IMIEB
R/W
RENESAS 241
1
0
IMIEA
R/W
0
0