HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 246

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Count
Direction
TCLKA pin
TCLKB pin
• Bit 5 (flag direction (FDIR)): FDIR selects the setting condition for the overflow flag (OVF) in
Bit 5: FDIR
0
1
• Bit 4 (PWM Mode 4 (PWM4)): PWM4 selects the PWM mode for channel 4. When the
Bit 4: PWM4
0
1
228 RENESAS
When the MDF is set to 1 to select the phase counting mode, the timer counter (TCNT2)
becomes an up/down counter and the TCLKA and TCLKB pins become count clock input
pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with the
increment/decrement chosen as follows:
In the phase counting mode, selections for external clock edge made in the CKEG1 and
CKEG0 bits of the timer control register 2 (TCR2) and the selection for counter clock made in
the TPSC2 –TPSC0 bits are ignored. The phase counting mode described above takes priority.
Settings for counter clear conditions in the CCLR1 and CCLR0 bits of TCR2 and settings for
timer I/O control register 2 (TIOR2), timer interrupt enable register (TIER2) and timer status
register 2 (TSR2) compare match/input capture functions and interrupts, however, are valid
even in the phase counting mode.
timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in.
PWM4 bit is set to 1 and the PWM mode entered, the TIOCA4 pin becomes a PWM output
pin. 1 is output on a compare match of general register A4 (GRA4); 0 is output on a compare
match of general register B4 (GRB4). When the complementary PWM mode or reset-
synchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control
register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0.
Rising
L
High
Rising
Decrement
Description
OVF of TSR2 is set to 1 when TCNT2 overflows or underflows (initial
value)
OVF of TSR2 is set to 1 when TCNT2 overflows
Description
Channel 4 operates normally (initial value)
Channel 4 operates in PWM mode
High
Falling
Low
Falling
Rising
High
High
Falling
Increment
Falling
Low
Low
Rising