HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 324

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.1.4
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Name
Port B control register 1
Port B control register 2
Port B data register
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Next data register A
Next data register B
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
11.2
11.2.1
The port B control register 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the
functions of port B pins. Port B consists of the dual use pins TP15–TP0. Bits corresponding to the
pins to be used for TPC output must be set to 1. For details, see the port B description in the
section 15, Pin Function Controller.
306 RENESAS
2. Bits used for TPC output cannot be written to.
3. These addresses change depending on TPCR settings. When TPC output groups 0
Registers
Register Descriptions
Port B Control Registers 1 and 2 (PBCR1, PCBR2)
details on the register addresses, see section 8.3.5, Description of Areas.
and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their
output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the
address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the
same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are
different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is
H'5FFFFF4.
Abbreviation
PBCR1
PBCR2
PBDR
TPMR
TPCR
NDERB
NDERA
NDRA
NDRB
R/W
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
2
Initial
Value
H'0000
H'0000
H'0000
H'F0
H'FF
H'00
H'00
H'00
H'00
Address*
H'5FFFFCC
H'5FFFFCE
H'5FFFFC2
H'5FFFFF0
H'5FFFFF1
H'5FFFFF2
H'5FFFFF3
H'5FFFFF5/
H'5FFFFF7*
H'5FFFFF4/
H'5FFFFF6*
1
3
3
Access
Size`
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16