HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 213

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Dual Address Mode
1. External memory and external memory transfer
2. External memory and memory-mapped external devices transfer
3. Memory-mapped external devices and memory-mapped external devices transfer
4. External memory and on-chip memory transfer
5. External memory and on-chip peripheral modules (excluding the DMAC) transfer
6. Memory-mapped external devices and on-chip memory transfer
7. Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC)
8. On-chip memory and on-chip memory transfer
9. On-chip memory and on-chip peripheral modules (excluding the DMAC) transfer
10. On-chip peripheral modules (excluding the DMAC) and on-chip peripheral modules
194 RENESAS
In the dual address mode, both the transfer source and destination are accessed (selectable) by
an address. The source and destination can be located externally or internally. The source is
accessed in the read cycle and the destination in the write cycle, so the transfer is performed in
two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8
shows an example of a transfer between two external memories in which data is read from one
memory in the read cycle and written to the other memory in the following write cycle.
In the dual address mode transfers, external memory, memory-mapped external devices, on-
chip memory and on-chip peripheral modules can be mixed without restriction. Specifically,
this enables the following transfer types:
transfer
(excluding the DMAC) transfer
SuperH microcomputer
Figure 9.8 Data Flow in Dual Address Mode
DMAC
1: Read cycle
2: Write cycle
External data bus
: Data flow
2
1
External
External
memory
memory

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