HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 394

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.8.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is
listed below.
1. SCI initialization: select the TxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1);
4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port
Figure 13.9 Example of Communication among Processors Using Multiprocessor Format
Serial
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared
automatically.
register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
data
Transmitting
processor A
processor
Receiving
(ID = 01)
MPB: multiprocessor bit
receiving processor address
(sending data H'AA to receiving processor A)
ID-sending cycle:
H'01
processor B
Receiving
(MPB = 1)
(ID = 02)
Serial communication line
processor specified by ID
data sent to receiving
Data-sending cycle:
processor C
Receiving
(ID = 03)
H'AA
(MPB = 0)
processor D
Receiving
(ID = 04)
RENESAS 377

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