HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 53

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Instruction codes, operation, and execution states are listed in the following format in order by
classification.
Table 2.11 Instruction Code Format
Item
Instruction
mnemonic
Instruction
code
Operation
summary
Execution
cycle
T bit
Note: Scaling ( 1, 2, 4) is performed according to the instruction operand size. See
30 RENESAS
"SH-1/SH-2 Programming Manual" for details.
Format
OP.Sz
MSB
(xx)
M/Q/T
&
|
^
~
<<n, >>n
,
LSB
SRC,DEST OP: Operation code
Explanation
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Direction of transfer
Memory operand
Flag bits in the SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Value when no wait states are inserted
Instruction execution cycles: The execution cycles shown in
the table are minimums. The actual number of cycles may
be increased:
1. When contention occurs between instruction fetches
2. When the destination register of the load instruction
Value of T bit after instruction is executed
No change
and data access, or
(memory
instruction are the same.
0000: R0
0001: R1
1111: R15
...........
register) and the register used by the next

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