HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 388

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
Serial transmit data is transmitted in the following order from the TxD pin:
1. Start bit: one 0 bit is output.
2. Transmit data: seven or eight bits of data are output, LSB first.
3. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is
4. Stop bit: one or two 1 bits (stop bits) are output.
5. Mark state: output of 1 bits continues until the start bit of the next transmit data.
6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode.
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the
SCI requests a transmit-data-empty interrupt (TXI) at this time.
output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then
continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
the SCR is set to 1, a transmit-end interrupt (TEI) is requested.
RENESAS 371