HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 135

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.3
8.3.1
Figure 8.3 shows the address format used in this LSI.
Since this LSI uses a 32-bit address, 4 Gbytes of space can be accessed on the architecture;
however, the upper 4 bits (A31–A28) are always ignored and not output. Bit A27 is basically only
used for switching the bus width. When the A27 bit is 0 (H'0000000–H'7FFFFFF), the bus width
is 8 bits; when the A27 bit is 1 (H'8000000–H'FFFFFFF), the bus width is 16 bits. Of the
remaining 27 bits (A26–A0), a total 128 Mbyte can thus be accessed.
The 128 Mbyte space is subdivided into 8 areas (areas 0–7) of 16 Mbytes each according to the
values of bits A26–A24. The space with bits A26–A24 as 000 is area 0 and the space 111 is area 7.
The A26–A24 bits are decoded and become the chip select signals (CS0–CS7) of the
corresponding areas 0–7 and output. Table 8.6 shows how the space is divided.
A31–A28 A27
Address Space Subdivision
Address Spaces and Areas
Ignore: Always ignore, not output externally
A26–A24
Basic bus width selection:
Not output externally, but used for basic bus width selection
When 0, (H'0000000–H'7FFFFFF), the basic bus width is 8 bits.
When 1, (H'8000000–H'FFFFFFF) the basic bus width is 16 bits.
Area selection:
Decoded to become chip select signals CS0–CS7 for areas 0–7
A23,A22
Figure 8.3 Address Format
4 Gbyte space
Ignore: Only valid when the address multiplex
function is being used in the DRAM space (area 1);
not output in other cases. When not output,
becomes shadow.
A21
128 Mbyte space
16 Mbyte space
Output address:
Output from address pins
A21–A0
4 Mbyte space
RENESAS 115
A0

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