HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 349

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit 5: TME
0
1
•
•
Bit 2:
CKS2
0
0
0
0
1
1
1
1
Note: The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
12.2.3
The RSTCSR is an eight-bit readable and writable register that controls output of the reset signal
generated by timer counter (TCNT) overflow and selects the internal reset signal type. The
RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4
Register Access, for details. RSTCR is initialized to H'1F by input of a reset signal from the RES
pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is
initialized to H'1F in standby mode.
Note: Only 0 can be written in bit 7 to clear the flag.
Bits 4 and 3 (reserved): These bits always read as 1. The write value should always be 1.
Bits 2–0 (clock Select 2–0 (CKS2–CKS0)): CKS2–CKS0 select one of eight internal clock
sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the
system clock ( ).
Initial value:
overflow occurs.
Bit name:
Reset Control/Status Register (RSTCSR)
R/W:
Bit 1:
CKS1
0
0
1
1
0
0
1
1
Bit:
WOVF
R/(W)*
7
0
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops (initial
value)
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt
is generated when TCNT overflows.
Bit 0:
CKS0
0
1
0
1
0
1
0
1
RSTE
R/W
6
0
Clock Source
RSTS
/2 (initial value)
/64
/128
/256
/512
/1024
/4096
/8192
R/W
5
0
—
—
4
1
Overflow Interval* ( = 20 MHz)
25.6 s
819.2 s
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
Description
—
—
3
1
—
—
2
1
—
—
RENESAS 331
1
1
—
—
0
1