HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 180

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2. Countermeasure against a spike on the BACK signal
160 RENESAS
The following describes the countermeasure against a spike on the BACK signal:
a. When BREQ is input to release the bus of the LSI, make sure that conflicts with a refresh
b. The spike on the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which
c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may be successful
operation do not occur. Stop the refresh operation or operate the refresh timer counter
(RTCNT) or the refresh time constant register (RTCOR) of the bus controller (BSC) to
shift the refresh timing.
can be eliminated by using a capacitor as shown in the figure below.
For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike
above 2.0 V.
Note that delay of the BACK signal increases approximately in units of 0.1 ns/pF. (When a
capacitance of 220 pF is added, the delay increases approximately by 22 ns.
or unsuccessful due to the narrow pulse width of the spike. Implement a circuit
configuration which will cause no problems when latching BACK or using BACK as a
trigger signal.
When splitting the BACK signal into two signals and latching each of them using the flip-
flop or triggering the flip-flop, the flip-flop may operate for one signal but may not for
another. To capture the BACK signal using the flip-flop, receive the BACK signal using a
single flip-flop then distribute the signal (see figure below).
Capacitor-incorporating circuit for eliminating a spike
SuperH
Microcomputer
BACK
C

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