HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 228

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6. Notes on use of the SLEEP command
In cases when the CPU does not carry out any other processing but is waiting for DMAC to end its
transfer during DMAC operation, do not use the SLEEP command, but use the transfer end flag bit
(TE) of the channel DMA control register and the polling software loop.
Phenomenon: If the bus cycle of DMAC is entered immediately after executing the SLEEP
command, the bus cycle of DMAC may conflict with that of CPU.
Accordingly, the bus cycle of DMAC which has conflicted with that of CPU may malfunction.
7. Sampling of DREQ
•
a. Operation contents
b. Countermeasure
If DREQ is set to level detection in the DMA cycle steal mode, sampling of DREQ may take
place before DACK is output. Note that some system configurations involve unnecessary
DMA transfers.
Operation
As shown in Figure 9.16, sampling of DREQ is carried out immediately before the leading
edge of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus
cycle where DACK is output.
If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be
carried out before DACK is output.
When the bus cycle of DMAC is entered immediately after executing the SLEEP
command, there are cases when the DMA transfer is carried out correctly.
• Stop the operation (for exemple, clearing of the DMA enable bit (DE) of the DMA
• When using DMAC during SLEEP, operate DMAC after releasing SLEEP through
channel control register(CHCRn)) before entering SLEEP.
interruption.
Address bus
Fetch cycle of
SLEEP command
CPU
CPU
This is in itself a DMAC cycle but
involves CPU operation.
CPU
DMAC
CPU
DMAC
CPU
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