HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 42
HD6477021X20V
Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6477021X20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.3
2.3.1
All instructions are RISC type. Their features are as follows:
16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more
efficient.
One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system.
One-cycle instructions are executed in 50 ns at 20 MHz.
Data Length: Long word is the standard data length for all operations. Memory can be accessed
in bytes, words, or long words. Byte or word data accessed from memory is sign-extended and
handled as long word data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations (handled as long word data).
Table 2.2
CPU of SH7000 Series
MOV.W @(disp,PC),R1
ADD
......................
..
.DATA.W
Note: The address of the immediate data is accessed by @(disp, PC).
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory, data is loaded to the registers and executed (load-store architecture). Instructions
such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption
during branching is reduced by first executing the instruction that follows the branch instruction,
and then branching. See the SH-1/SH-2 Programming Manual for details.
Table 2.3
CPU of SH7000 Series
BRA
ADD
Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip
multiplier enable 16-bit
16-bit 16-bit + 42-bit
R1,R0
TRGET
R1, R0
Instruction Features
RISC-Type Instruction Set
Sign Extension of Word Data
Delayed Branch Instructions
H'1234
16-bit
42-bit multiplication/accumulation operations can be executed in 2–3
Description
Data is sign-extended to 32 bits, and
R1 becomes H'00001234. It is next
operated upon by an ADD instruction.
Description
Executes an ADD before
branching to TRGET.
32-bit multiplication operations to be executed in 1–3 cycles.
Conventional CPU
ADD.W R1, R0
BRA
Conventional CPUs
ADD.W #H'1234, R0
TRGET
RENESAS19
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