HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 247

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

•
Bit 3: PWM3
0
1
•
Bit 2: PWM2
0
1
•
Bit 1: PWM1
0
1
•
Bit 0: PWM0
0
1
Bit 3 (PWM Mode 3 (PWM3)): PWM3 selects the PWM mode for channel 3. When the
PWM3 bit is set to 1 and the PWM mode entered, the TIOCA3 pin becomes a PWM output
pin. 1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare
match of general register B3 (GRB3). When the complementary PWM mode or reset-
synchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control
register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0.
Bit 2 (PWM Mode 2 (PWM2)): PWM2 selects the PWM mode for channel 2. When the
PWM2 bit is set to 1 and the PWM mode entered, the TIOCA2 pin becomes a PWM output
pin. 1 is output on a compare match of general register A2 (GRA2); 0 is output on a compare
match of general register B2 (GRB2).
Bit 1 (PWM Mode 1 (PWM1)): PWM1 selects the PWM mode for channel 1. When the
PWM1 bit is set to 1 and the PWM mode entered, the TIOCA1 pin becomes a PWM output
pin. 1 is output on a compare match of general register A1 (GRA1); 0 is output on a compare
match of general register B1 (GRB1).
Bit 0 (PWM Mode 0 (PWM0)): PWM0 selects the PWM mode for channel 0. When the
PWM0 bit is set to 1 and the PWM mode entered, the TIOCA0 pin becomes a PWM output
pin. 1 is output on a compare match of general register A0 (GRA0); 0 is output on a compare
match of general register B0 (GRB0).
Description
Channel 3 operates normally (initial value)
Channel 3 operates in PWM mode
Description
Channel 2 operates normally (initial value)
Channel 2 operates in PWM mode
Description
Channel 1 operates normally (initial value)
Channel 1 operates in PWM mode
Description
Channel 0 operates normally (initial value)
Channel 0 operates in PWM mode
RENESAS 229