HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 197

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK
Bit 7: AM
0
1
• Bit 6 (acknowledge Level Bit (AL)): AL selects active high signal or active low signal for the
Bit 6: AL
0
1
• Bit 5 (DREQ select bit (DS)): DS selects the DREQ input detection method used. This bit is
Bit 5: DS
0
1
• Bit 4 (transfer bus mode bit (TM)): TM selects the bus mode for DMA transfers. The TM bit is
Bit 4: TM
0
1
178 RENESAS
signal is output during the data read cycle or write cycle. This bit is valid only in channels 0
and 1. The AM bit is initialized to 0 by resets or in standby mode. The AM bit is not valid in
single address mode.
DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by resets
or in standby mode.
valid only in channels 0 and 1. The DS bit is initialized to 0 by resets or in standby mode.
initialized to 0 by resets or in standby mode. When the source of the transfer request is an on-
chip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes
with the RS Bit.
Description
DACK is output in read cycle (initial value)
DACK is output in write cycle
Description
DACK is active high (initial value)
DACK is active low
Description
DREQ detected by low level (initial value)
DREQ detected by falling edge
Description
Cycle-steal mode (initial value)
Burst mode

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