HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 365

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.2.6
The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in
the asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock
source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a reset or
in standby mode.
• Bit 7 (transmit interrupt enable (TIE)): TIE enables or disables the transmit-data-empty
Bit 7: TIE
0
1
• Bit 6 (receive interrupt enable (RIE)): RIE enables or disables the receive-data-full interrupt
Bit 6: RIE
0
1
RENESAS 348
interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status
register (SSR) is set to 1 due to transfer of serial transmit data from the TDR to the TSR.
(RXI) requested when the receive data register full bit (RDRF) in the serial status register
(SSR) is set to 1 due to transfer of serial receive data from the RSR to the RDR. Also enables
or disables receive-error interrupt (ERI) requests.
Initial value:
Bit name:
Serial Control Register
R/W:
Bit:
R/W
TIE
7
0
Description
Transmit-data-empty interrupt request (TXI) is disable. The TXI
interrupt request can be cleared by reading TDRE after it has been set
to 1, then clearing TDRE to 0, or by clearing TIE to 0 (initial value).
Transmit-data-empty interrupt request (TXI) is enabled
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are disabled. RXI and ERI interrupt requests can be cleared
by reading the RDRF flag or error flag (FER, PER, or ORER) after it
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0
(initial value).
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are enabled
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
CKE0
R/W
0
0

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