HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 386

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Transmitting Serial Data (asynchronous mode): Figure 13.5 shows a sample flowchart for
transmitting serial data. The procedure for transmitting serial data is as follows:
1. SCI initialization: select the TxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1);
4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port
Note:
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to
0.
if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared
automatically.
register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
Circled numbers refer to the preceding procedure.
Figure 13.4 Sample Flowchart for SCI Initialization
Select communication format in SMR
Set TE or RE to 1 in SCR; Set RIE,
TIE, TEIE, and MPIE as necessary
Clear TE and RE bits to 0 in SCR
Set CKE1 and CKE0 bits in SCR
(leaving TE and RE cleared to 0)
1-bit interval elapsed?
Start of initialization
Set value in BRR
End
Yes
Wait
No
(1)
(2)
(3)
(4)
RENESAS 369

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