HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 414

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

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Cautions for Clocked Synchronous External Clock Mode:
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Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF = 1 when RE
is set to zero 1.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to
RDR.
Note:
When using an external clock source for the serial clock, update the TDR with the DMAC, and
then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input
in the first four system clocks after the TDR is written, an error may occur (figure 13.22).
Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source using the resource select bit (RS) in the channel control
register (CHCR).
Set TE = RE = 1 only when the external clock SCI is 1.
Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0
to 1.
When receiving, RDRF = 1 when RE is set to zero 2.5–3.5 clocks after the rise edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
TDRE
SCK
Figure 13.22 Clocked Synchronous Transmitting Example with DMAC
During external clock operation, an error may occur if t is 4 or less.
t
D0
D1
D2
D3
D4
D5
D6
RENESAS 397
D7