UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 234

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Clock operation status control register (CSC)
232
This register is used to control the operations of the high-speed system clock
clock, and subsystem clock (except the 40 MHz internal high-speed oscillation clock and internal low-speed
oscillation clock).
CSC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Note
Address: FFFA1H
Symbol
CSC
The 78K0R/IB3 doesn’t have the subsystem clock.
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
Notes 1.
XTSTOP
HIOSTOP
MSTOP
MSTOP
<7>
Figure 5-5. Format of Clock Operation Status Control Register (CSC)
0
1
0
1
0
1
2.
Note 1
After reset: C0H
2. To start X1 oscillation as set by MSTOP, check the oscillation stabilization time
3. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the
4. Do not stop the clock selected for the CPU peripheral hardware clock (f
5. The setting of the flags of the register to stop clock oscillation (invalidate the
6. Set the oscillation stabilization time select register (OSTS) before setting the
XTSTOP bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 6 is fixed to 0.
The 8 MHz (TYP.) internal high-speed oscillation clock stops. Stopping the internal high-
speed oscillator (HIOSTOP = 1) is prohibited while the 40 MHz internal high-speed
oscillation clock is operating (DSCON = 1).
oscillation clock by using the 40 MHz internal high-speed oscillation control register
(DSCCTL) and not the HIOSTOP bit.
X1 oscillator operating
X1 oscillator stopped
XT1 oscillator operating
XT1 oscillator stopped
Internal high-speed oscillator operating
Internal high-speed oscillator stopped
XTSTOP
setting CSC.
of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
subsystem clock to stabilize by setting a wait time using software.
the OSC register.
external clock input) and the condition before clock oscillation is to be stopped
are as Table 5-3.
MSTOP bit to 0 after releasing reset. Note that if the OSTS register is being used
with its default settings, the OSTS register is not required to be set here.
<6>
X1 oscillation mode
Note 1
XT1 oscillation mode
CHAPTER 5 CLOCK GENERATOR
R/W
User’s Manual U19678EJ1V1UD
5
0
Internal high-speed oscillation clock operation control
High-speed system clock operation control
Subsystem clock operation control
External clock from EXCLK
pin is valid
External clock from EXCLK
pin is invalid
4
0
External clock input mode
Note 2
3
0
Input port
Stop the 40 MHz internal high-speed
2
0
Note
Input port mode
Input port
, internal high-speed oscillation
Input port mode
1
0
HIOSTOP
<0>
CLK
) with