UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 738

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

736
(2) Operation procedure
Caution
Changing setting of SOE0 register
After setting the SAU0EN bit of peripheral enable register 0 (PER0) to 1, be sure to set
serial clock select register 0 (SPS0) after 4 or more f
Figure 13-94. Initial Setting Procedure for Address Field Transmission
Starting communication
Setting SMR02 register
Setting SCR02 register
Setting SDR02 register
Writing to SS0 register
Setting PER0 register
Setting SPS0 register
Starting initial setting
Setting SO0 register
Setting SO0 register
Setting SO0 register
Setting port
Wait
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
Set the initial output level of the serial
data (SO02) and serial clock (CKO02).
Enable data output, clock output, and N-ch
open-drain output (V
target channel by setting the port register, port
mode register, and port output mode register.
Set the SS02 bit of the target channel to 1
and set SE02 bit to 1 (to enable operation).
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f
Clear the SO02 bit to 0 to generate the
start condition.
Secure a wait time so that the specifications of
I
Clear the CKO02 bit to 0 to lower the
clock output level.
Set the SOE02 bit to 1 and enable data
output of the target channel.
Set address and R/W to the SIO10
register (bits 7 to 0 of the SDR02
register) and start communication.
2
C on the slave side are satisfied.
MCK
)).
DD
tolerance) mode of the
CLK
clocks have elapsed.