UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 713

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(Note, Caution, and Remark are listed on the next page.)
(1) Register setting
SMR0n
Operation clock (f
channel n
0: Prescaler output clock CK00
1: Prescaler output clock CK01
SCR0n
SDR0n
SMR0r
set by SPS0 register
set by SPS0 register
SO0
(a) Serial mode register 0n (SMR0n)
(b) Serial mode register 0r (SMR0r)
(c) Serial communication operation setting register 0n (SCR0n)
(e) Serial output register 0 (SO0)
(d) Serial data register 0n (SDR0n) (lower 8 bits: RXDq)
Same setting value as CKS0n bit
CKS0n
TXE0n
CKS0r
0/1
0/1
15
15
15
15
15
0
0
Figure 13-79. Example of Contents of Registers for UART Reception of UART
Setting of parity bit
00B: No parity
01B: No parity judgment
10B: Appending Even parity
11B: Appending Odd parity
CCS0n
RXE0n
CCS0r
MCK
14
14
14
14
14
0
0
1
0
) of
DAP0n
13
13
13
13
13
0
0
0
0
Baud rate setting
CKP0n
12
12
12
12
12
0
0
0
0
0: Forward (normal) reception
1: Reverse reception
11
11
11
11
11
0
0
0
1
CHAPTER 13 SERIAL ARRAY UNIT
EOC0n
CKO02
10
10
10
10
10
0
1
0
×
User’s Manual U19678EJ1V1UD
(UART0, UART1) (1/2)
PTC0n1
CKO01
×
0/1
0
9
9
0
9
9
9
Note
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
PTC0n0
STS0n
CKO00
STS0r
×
0/1
1
8
8
0
8
0
8
8
Note
DIR0n
0/1
7
0
7
0
7
0
7
7
SIS0n0
SIS0r0
0/1
0
6
0
0
6
6
6
6
SLC0n1
1
1
0
0
5
5
5
5
5
Receive data register
SLC0n0
1
4
0
4
0
4
4
0
4
RXDq
Interrupt source of channel n
Interrupt source of channel n
0
3
0
3
0
3
3
1
3
1: Buffer empty interrupt
0: Transfer end interrupt
0: Transfer end interrupt
Setting of data length
DLS0n2
MD0n2
MD0r2
SO02
2
0
2
0
2
1
×
2
2
MD0n1
DLS0n1
MD0r1
SO01
×
0/1
1
1
1
1
1
1
1
Note
MD0n0
DLS0n0
MD0r0
SO00
0/1
0/1
0
×
0
0
0
0
0
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