UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 293
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UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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(b) Start timing in event counter mode
(c) Start timing in capture mode
Caution In the first cycle operation of count clock after writing TSn, an error at a maximum of one
<1> TCRn holds its initial value while operation is stopped (TEn = 0).
<2> Operation is enabled (TEn = 1) by writing 1 to the TSn.
<3> 1 is written to TSn and 1 is set to TEn, and at the same time the value of TDRn is loaded to TCRn to
<4> After that, the TCRn value is counted down according to the count clock.
<1> Operation is enabled (TEn = 1) by writing 1 to the TSn.
<2> The write data to TSn is held until count clock generation.
<3> TCRn holds the initial value until count clock generation.
<4> On generation of count clock, 0000H is loaded to TCRn and count starts.
start counting.
Start trigger detection signal
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MDn0 = 1.
Start trigger detection signal
TSn (write) hold signal
TSn (write) hold signal
Count clock
TSn (write)
Count clock
TSn (write)
Figure 6-12. Start Timing (In Event Counter Mode)
INTTMn
Figure 6-13. Start Timing (In Capture Mode)
TCRn
TCRn
TEn
f
TEn
CLK
f
CLK
CHAPTER 6 TIMER ARRAY UNIT TAUS
<1>
<1>
Initial value
User’s Manual U19678EJ1V1UD
<1>
<2>
<2>
Initial value
<3>
<3>
TDRn value
When MDn0 = 1 is set
0000H
TDRn value-1
<4>
291
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