UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 788

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.6 Wait
receive data (in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
786
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE = 1)
Transfer lines
Master
Slave
ACKE
SDA0
SCL0
SCL0
SCL0
IICA
IICA
H
D2
CHAPTER 14 SERIAL INTERFACE IICA
6
6
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
D1
7
7
User’s Manual U19678EJ1V1UD
Figure 14-20. Wait (1/2)
D0
8
8
Wait from slave
9
ACK
Wait after output
of ninth clock
9
FFH is written to IICA or WREL is set to 1
Wait from master
IICA data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3