UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 719

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6.3 LIN transmission
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
designed to reduce the cost of an automobile network.
receives this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%,
communication can be established.
Remark
Support of LIN communication
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART transmission, UART0 supports LIN communication.
For LIN transmission, channel 0 of unit (SAU) is used.
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave
Figure 13-85 outlines a transmission operation of LIN.
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
f
f
MCK
CLK
UART
: System clock frequency
: Operation clock frequency of target channel
Supported
TxD0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
None
8 bits
Max. f
Reverse output (default: low level)
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
Channel 0 of SAU
Forward output (default: high level)
The following selectable
MCK
/6 [bps] (SDR00 [15:9] = 2 or more), Min. f
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
UART0
Not supported
CLK
/(2 × 2
11
× 128) [bps]
UART1
−
−
−
Note
717