UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 623

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03)
(6) Serial flag clear trigger register 0n (SIR0n)
Symbol
SIR0n
SIR0n register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECT0n, PECT0n, OVCT0n) of this register is set to 1, the corresponding bit (FEF0n, PEF0n,
OVF0n) of serial status register 0n is cleared to 0. Because SIR0n register is a trigger register, it is cleared
immediately when the corresponding bit of SSR0n register is cleared.
SIR0n register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIR0n register can be set with an 8-bit memory manipulation instruction with SIR0nL.
Reset signal generation clears SIR0n register to 0000H.
Caution Be sure to clear bits 15 to 3 to “0”.
Remarks 1. n: Channel number (n = 0 to 3)
OVC
PEC
FEC
T0n
T0n
T0n
15
0
1
0
1
0
1
0
2. When the SIR0n register is read, 0000H is always read.
Not cleared
Clears the FEF0n bit of the SSR0n register to 0.
Not cleared
Clears the PEF0n bit of the SSR0n register to 0.
Not cleared
Clears the OVF0n bit of the SSR0n register to 0.
14
0
Figure 13-9. Format of Serial Flag Clear Trigger Register 0n (SIR0n)
13
0
12
0
CHAPTER 13 SERIAL ARRAY UNIT
11
0
User’s Manual U19678EJ1V1UD
10
Clear trigger of overrun error flag of channel n
0
Clear trigger of parity error flag of channel n
Clear trigger of framing error of channel n
9
0
After reset: 0000H
8
0
7
0
6
0
R/W
5
0
4
0
3
0
FEC
T0n
2
PEC
T0n
1
OVC
T0n
621
0