UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 659

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 13-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAP0n = 0, CKP0n = 0)
register 0n
SCKp pin
(4) Processing flow (in continuous reception mode)
INTCSIp
MD0n0
TSF0n
SDR0n
BFF0n
SIp pin
SS0n
SE0n
ST0n
Shift
Caution The MD0n0 bit of serial mode register 0n (SMR0n) can be rewritten even during operation.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 13-39 Flowchart of Master
<1> <2>
However, rewrite it before receive of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last receive data.
2. n: Channel number (n = 0 to 2) (n = 2 (78K0R/IB3 and 38-pin products of 78K0R/IC3), n = 0 to 2
Reception (in Continuous Reception Mode).
(44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3))
p: CSI number (p = 00, 01, 10) (p = 10(78K0R/IB3 and 38-pin products of 78K0R/IC3), p = 00,
01, 10 (44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3))
Write
<3>
Dummy data
Data reception (8-bit length)
Reception & shift operation
Receive data 1
<2>
Write
Dummy data
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
<3>
Receive data 1
Data reception (8-bit length)
Reception & shift operation
Receive data 2
<4> <2>
Read
Write
Dummy data
<3>
Reception & shift operation
<4>
Receive data 2
Data reception (8-bit length)
Receive data 3
Read
<5>
Receive data 3
Read
<6>
<7> <8>
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