UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 579
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
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Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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(6) Successive approximation register (SAR)
(7) 10-bit A/D conversion result register (ADCR)
(8) 8-bit A/D conversion result register (ADCRH)
(9) Controller
(10) AV
(11) AV
The SAR register is a 12-bit register that sets voltage tap data whose values from the array match the voltage
values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents
of the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the
specified A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is
generated.
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6
bits are fixed to 0).
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as
well as starting and stopping of the conversion operation. When A/D conversion has been completed, this
controller generates INTAD.
This pin inputs the reference voltage of the A/D converter, the programmable gain amplifier, the power supply
pins and A/D converter of the comparator, and the comparator. When all pins of ports 2, 8, and 15 are used as
the analog port pins, make the potential of AV
pins of ports 2, 8, and 15 are used as the digital port pins, make AV
The analog signal input to ANI0 to ANI11 is converted into a digital signal, based on the voltage applied across
AV
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the V
pin even when the A/D converter is not used.
Remark
REF
REF
SS
pin
and AV
pin
ANI0 to ANI5
ANI0 to ANI7
ANI0 to ANI9
ANI0 to ANI10 : 48-pin products of 78K0R/IC3 and 78K0R/ID3
ANI0 to ANI11 : 78K0R/IE3
SS
.
: 78K0R/IB3
: 38-pin products of 78K0R/IC3
: 44-pin products of 78K0R/IC3
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
REF
be such that 2.7 V ≤ AV
REF
the same potential as V
REF
≤ V
DD
. When one or more of the
DD
.
577
SS
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