UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 488

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UPD78F1203MC-CAB-AX

Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1203MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
Remark
486
Figure 7-84. Operation Procedure When Non-complementary Modulation Output Function (Type 1) Is Used (2/2)
Operation
start
During
operation
Operation
stop
TAUS
stop
m = 02 to 07
Sets TOEm (slaves 2 to 7) to 1 (only when operation is
resumed).
The TS00 (master), TS01 (slave 1), and TSm (slaves 2
to 7) bits of the TS0 register are set to 1 at the same
time.
Set values of the TDR00, TDR01, and TDRm registers
can be changed after INTTM00 of the master channel is
generated.
The TCR00, TCR01, and TCRm registers can always be
read.
Set values of the TROm and TMEm registers can be
changed.
The TT00 (master), TT01 (slave 1), and TTm (slaves 2
to 7) bits are set to 1 at the same time.
The TOEm bits of slave channels 2 to 7 are cleared to 0
and value is set to the TOm bit.
To hold the TOm pin output level
When holding the TOm pin output level is not necessary
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
The TS00, TS01, and TSm bits automatically return to
0 because they are trigger bits.
The TT00, TT01, and TTm bits automatically return to
0 because they are trigger bits.
Clears the TOm bit to 0 after the value to be held is
set to the port register.
Switches the port mode register to input mode.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
TE00 = 1, TE01 = 1, TEm = 1
6-phase PWM output is performed by the master channel
and slave channels 2 to 7.
At slave channel 1, the values of the TDR01 register are
transferred to TCR01, triggered by INTTM00 of the master
channel, and the counter starts counting down.
Slave channels 2 to 7 perform real-time output by using the
INTTM01 signal of slave channel 1.
modulation output of the PWM and real-time outputs is
performed according to setting of TMEm.
After that, the above operation is repeated.
TE00, TE01, TEm = 0, and count operation stops.
The TOm pin outputs the TOm set level.
The TOm pin output level is held by port function.
The TOm pin output level goes into Hi-Z output state.
Power-off status
When the master channel starts counting, INTTM00 is
generated. Triggered by this interrupt, the slave channels
1 to 7 also start counting.
TCR00, TCR01, and TCRm hold count value and stops.
The TOm output is not initialized but holds current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TOm bit is cleared to 0 and the TOm pin is set to port
mode.)
Hardware Status
Non-complementary

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