UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 783

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.2 Setting transfer clock by using IICWL and IICWH registers
(1) Setting transfer clock on master side
(2) Setting IICWL and IICWH on slave side
Caution Note the minimum f
Remarks 1. Calculate the rise time (t
At this time, the optimal setting values of IICWL and IICWH are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
• When the normal mode
(The fractional parts of all setting values are truncated.)
• When the fast mode
• When the normal mode
Transfer clock =
IICWL =
IICWH = (
IICWL =
IICWH = (
IICWL = 1.3
IICWH = (1.2
IICWL = 4.7
IICWH = (5.3
2. IICWL: IICA low-level width setting register
operation frequency for serial interface IICA is determined according to the mode.
Fast mode:
Normal mode: f
they differ depending on the pull-up resistance and wire load.
IICWH: IICA high-level width setting register
t
t
f
F
R
CLK
:
:
Transfer clock
Transfer clock
:
Transfer clock
Transfer clock
μ
μ
IICWL + IICWH + f
μ
μ
s × f
s × f
SDA0 and SCL0 signal falling times
SDA0 and SCL0 signal rising times
CPU/peripheral hardware clock frequency
0.52
0.47
s − t
s − t
0.48
0.53
CLK
CLK
R
R
− t
− t
f
F
F
CLK
CLK
CLK
) × f
) × f
× f
× f
f
CHAPTER 14 SERIAL INTERFACE IICA
− t
− t
CLK
CLK
CLK
= 3.5 MHz (MIN.)
= 1 MHz (MIN.)
operation frequency when setting the transfer clock. The minimum f
CLK
CLK
R
R
− t
− t
R
CLK
) and fall time (t
F
F
User’s Manual U19678EJ1V1UD
) × f
) × f
(t
R
CLK
CLK
+ t
F
)
F
) of the SDA0 and SCLA0 signals separately, because
781
CLK