UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 846

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4.2 Division operation
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• Initial setting
• During operation processing
• Operation end
• Next operation
<1> Set bit 7 (DIVMODE) of the multiplication/division control register (MDUC) to 1.
<2> Set the dividend (higher 16 bits) to the multiplication/division data register A (H) (MDAH).
<3> Set the dividend (lower 16 bits) to the multiplication/division data register A (L) (MDAL).
<4> Set the divisor (higher 16 bits) to the multiplication/division data register B (H) (MDBH).
<5> Set the divisor (lower 16 bits) to the multiplication/division data register B (L) (MDBL).
<6> Set bit 0 (DIVST) of MDUC to 1.
<7> The operation will end when one of the following processing is completed.
<8> DIVST is cleared (0) and an interrupt request signal (INTMD) is generated (end of operation).
<9> Read the quotient (lower 16 bits) from MDAL.
<10> Read the quotient (higher 16 bits) from MDAH.
<11> Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL).
<12> Read the remainder (higher 16 bits) from the multiplication/division data register C (H) (MDCH).
<13> To execute multiplication operation next, start from the “Initial setting” in 15.4.1 Multiplication operation.
<14> To execute division operation next, start from the “Initial setting” for division operation.
Remark
(There is no preference in the order of executing steps <2> to <5>.)
• A wait of at least 16 clocks (The operation will end when 16 clocks have been issued.)
• A check whether DIVST has been cleared
• Generation of a division completion interrupt (INTMD)
(The read values of MDBL, MDBH, MDCL, and MDCH during operation processing are not guaranteed.)
(There is no preference in the order of executing steps <9> to <12>.)
Steps <1> to <12> correspond to <1> to <12> in Figure 15-7.
CHAPTER 15 MULTIPLIER/DIVIDER
User’s Manual U19678EJ1V1UD