UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 354

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

352
Operation
start
During
operation
Operation
stop
TAUS
stop
Remark
Sets TOEm (slave) to 1 (only when operation is
resumed).
The TSn (master) and TSm (slave) bits of the TS0
register are set to 1 at the same time.
Set values of the TMRn and TMRm registers, TOMn,
TOMm, TOLn, and TOLm bits cannot be changed.
Set values of the TDRn and TDRm registers can be
changed after INTTMn of the master channel is
generated.
The TCRn and TCRm registers can always be read.
The TSRn and TSRm registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TTn (master) and TTm (slave) bits are set to 1 at the
same time.
TOEm of slave channel is cleared to 0 and value is set to
the TOm bit.
To hold the TOm pin output level
When holding the TOm pin output level is not
necessary
The TAU0EN bit of the PER2 register is cleared to 0.
Switches the port mode register to input mode.
n = 00, 02, 04, 06, 08, 10 (78K0R/IB3: n = 02, 04, 06 and 10)
m = n + 1
The TSn and TSm bits automatically return to 0
because they are trigger bits.
The TTn and TTm bits automatically return to 0
because they are trigger bits.
Clears TOm bit to 0 after the value to
be held is set to the port register.
Figure 6-65. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
TEn = 1, TEm = 1
The counter of the master channel loads the TDRn value
to TCRn, and counts down. When the count value
reaches TCRn = 0000H, INTTMn output is generated. At
the same time, the value of the TDRn register is loaded to
TCRn, and the counter starts counting down again.
At the slave channel, the value of TDRm is loaded to
TCRm, triggered by INTTMn of the master channel, and
the counter starts counting down. The output level of
TOm becomes active one count clock after generation of
the INTTMn output from the master channel. It becomes
inactive when TCRm = 0000H, and the counting operation
is stopped.
After that, the above operation is repeated.
TEn, TEm = 0, and count operation stops.
The TOm pin outputs the TOm set level.
The TOm pin output level is held by port function.
The TOm pin output level goes into Hi-Z output state.
Power-off status
When the master channel starts counting, INTTMn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
TCRn and TCRm hold count value and stops.
The TOm output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOm bit is cleared to 0 and the TOm pin is set to
port mode.)
Hardware Status