UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 799

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SDA0
SCL0
Figure 14-25 shows the communication reservation timing.
Remark
Communication reservations are accepted via the timing shown in Figure 14-26. After bit 1 (STD) of the IICA
status register (IICS) is set to 1, a communication reservation can be made by setting bit 1 (STT) of IICA
control register 0 (IICCTL0) to 1 before a stop condition is detected.
Figure 14-27 shows the communication reservation protocol.
SDA0
SCL0
SPD
STD
Hardware processing
Program processing
1
IICA:
STT:
STD:
SPD:
2
Standby mode (Communication can be reserved by setting STT to 1 during this period.)
Figure 14-26. Timing for Accepting Communication Reservations
3
Bit 1 of IICA control register 0 (IICCTL0)
IICA shift register
Bit 1 of IICA status register (IICS)
Bit 0 of IICA status register (IICS)
STT = 1
Communi-
cation
reservation
4
Figure 14-25. Communication Reservation Timing
5
CHAPTER 14 SERIAL INTERFACE IICA
6
User’s Manual U19678EJ1V1UD
7
Generate by master device with bus mastership
8
9
Set SPD
and
INTIICA
Write to
IICA
Set
STD
1
2
3
4
5
797
6