UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 785

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.2 Addresses
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
data matches the data values stored in the slave address register (SVA). If the address data matches the SVA values,
the slave device is selected and communicates with the master device until the master device generates a start
condition or stop condition.
14.5.3 Transfer direction specification are written to the IICA shift register (IICA). The received addresses are
written to IICA.
14.5.3 Transfer direction specification
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
The slave address is assigned to the higher 7 bits of IICA.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
INTIICA
INTIICA
SDA0
SCL0
SDA0
SCL0
Figure 14-17. Transfer Direction Specification
A6
A6
1
CHAPTER 14 SERIAL INTERFACE IICA
1
A5
A5
2
2
User’s Manual U19678EJ1V1UD
Figure 14-16. Address
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
A1
Transfer direction specification
A1
6
6
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note
783