UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 239

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) 40 MHz internal high-speed oscillation control register (DSCCTL)
Note Bit 3 is read-only.
Cautions 1. Set the DSCON bit when V
This register controls the 40 MHz internal high-speed oscillation clock (DSC) function.
This register can be used to control oscillation of the 40 MHz internal high-speed oscillation clock (f
the 40 MHz internal high-speed oscillation clock (f
DSCCTL can be set by a 1-bit manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F6H
DSCCTL
Symbol
Figure 5-8. Format of 40 MHz Internal High-speed Oscillation Control Register (DSCCTL)
2. The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1.
set the SELDSC bit.
SELDSC
DSCON
DSCS
DSPO
7
0
0
1
0
1
0
1
0
1
After reset: 00H
Not supplied
Supplied (The CPU/peripheral hardware clock (f
speed oscillation clock.)
Does not select 40 MHz internal high-speed oscillation (clock selected by the system clock
control register (CKC) is supplied to f
Selects 40 MHz internal high-speed oscillation (40 MHz internal high-speed oscillation is
supplied to f
Other than when f
When f
(Supplies a clock of f
f
Stopped
Operating
CLK
Selection of 40 MHz internal high-speed oscillation for CPU/peripheral hardware clock (f
/2 to a CPU or peripheral hardware not supporting 40 MHz.)
6
0
CLK
Operating or stopping 40 MHz internal high-speed oscillation clock (f
= 40 MHz (TYP.)
CLK
CHAPTER 5 CLOCK GENERATOR
R/W
)
CLK
User’s Manual U19678EJ1V1UD
Note
40 MHz internal high-speed oscillation supply status flag
5
0
DD
CLK
= 40 MHz (TYP.)
≥ 2.7 V, set the DSPO bit when 100
to peripheral hardware supporting 40 MHz and supplies a clock of
IH40
) as the CPU/peripheral hardware clock.
40 MHz operation selection bit
4
0
CLK
)
DSCS
3
CLK
) operates on the 40 MHz internal high-
SELDSC
2
μ
s have elapsed, and then
DSPO
1
IH40
)
IH40
DSCON
CLK
) and select
0
)
237