UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 900

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UPD78F1203MC-CAB-AX

Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1203MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
898
Address: FFFA2H
Symbol
OSTC
Figure 18-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8
MOST
MOST
7
8
8
0
1
1
1
1
1
1
1
1
MOST
MOST
After reset: 00H
6
9
9
0
0
1
1
1
1
1
1
1
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time
X
: X1 clock oscillation frequency
and remain 1.
stabilization time set by OSTS.
released while the internal high-speed oscillation clock is being used as the
CPU clock, set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time
set by OSTS is set to OSTC after STOP mode is released.
until clock oscillation starts (“a” below).
MOST
MOST
10
10
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization
5
0
0
0
1
1
1
1
1
1
X1 pin voltage
waveform
time set by OSTS
MOST
MOST
CHAPTER 18 STANDBY FUNCTION
11
11
4
0
0
0
0
1
1
1
1
1
R
User’s Manual U19678EJ1V1UD
MOST
MOST
STOP mode release
13
13
3
0
0
0
0
0
1
1
1
1
MOST
MOST
15
15
2
0
0
0
0
0
0
1
1
1
a
MOST
MOST
17
17
1
0
0
0
0
0
0
0
1
1
If the STOP mode is entered and then
MOST
MOST
18
18
0
0
0
0
0
0
0
0
0
1
2
2
2
2
2
2
2
2
2
8
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
/f
Oscillation stabilization time status
X
X
X
X
X
X
X
X
X
max. 25.6
min. 25.6
min. 51.2
min. 102.4
min. 204.8
min. 819.2
min. 3.27 ms min.
min. 13.11 ms min. 6.55 ms min.
min. 26.21 ms min. 13.11 ms min.
f
X
= 10 MHz
μ
μ
μ
μ
μ
μ
s max.
s min.
s min.
s min. 51.2
s min. 102.4
s min. 409.6
12.8
12.8
25.6
1.64 ms min.
f
X
= 20 MHz
μ
μ
μ
μ
μ
μ
s max.
s min.
s min.
s min.
s min.
s min.

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