UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 934

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
21.4.1 When used as reset
(1) When detecting level of supply voltage (V
932
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
• When starting operation
signal when V
generates an internal reset signal when EXLVI < V
V
V ±0.1 V). When EXLVI drops lower than V
(EXLVI ≥ V
LVI
<1>
<2>
<3>
<4>
(V
DD
LVISEL: Bit 2 of LVIM
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
(V
selection register (LVIS).
< V
EXLVI
DD
LVI
)) (default value).
DD
) or when V
), generates an interrupt signal (INTLVI).
< V
LVI
, and releases internal reset when V
DD
becomes V
CHAPTER 21 LOW-VOLTAGE DETECTOR
User’s Manual U19678EJ1V1UD
LVI
DD
or higher (V
)
EXLVI
DD
DD
) and detection voltage (V
EXLVI
(EXLVI < V
) and detection voltage (V
, and releases internal reset when EXLVI ≥ V
DD
≥ V
DD
≥ V
LVI
EXLVI
), generates an interrupt signal (INTLVI).
LVI
) or when EXLVI becomes V
.
LVI
LVI
). When V
), generates an internal reset
DD
drops lower than
EXLVI
EXLVI
EXLVI
or higher
.
= 1.21
EXLVI
),