MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 109

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.6.4.1 Breakpoint Acknowledge Cycle
MC68336/376
USER’S MANUAL
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with background debug mode. In
M68300 microcontrollers, both hardware and software can initiate breakpoints.
The CPU32 BKPT instruction allows the user to insert breakpoints through software.
The CPU responds to this instruction by initiating a breakpoint acknowledge read cycle
in CPU space. It places the breakpoint acknowledge (%0000) code on ADDR[19:16],
the breakpoint number (bits [2:0] of the BKPT opcode) on ADDR[4:2], and %0 (indi-
cating a software breakpoint) on ADDR1.
External breakpoint circuitry decodes the function code and address lines and re-
sponds by either asserting BERR or placing an instruction word on the data bus and
asserting DSACK. If the bus cycle is terminated by DSACK, the CPU32 reads the in-
struction on the data bus and inserts the instruction into the pipeline. (For 8-bit ports,
this instruction fetch may require two read cycles.)
If the bus cycle is terminated by BERR, the CPU32 then performs illegal instruction
exception processing: it acquires the number of the illegal instruction exception vector,
computes the vector address from this number, loads the content of the vector address
into the PC, and jumps to the exception handler routine at that address.
Assertion of the BKPT input initiates a hardware breakpoint. The CPU32 responds by
initiating a breakpoint acknowledge read cycle in CPU space. It places the breakpoint
acknowledge code of %0000 on ADDR[19:16], the breakpoint number value of %111
on ADDR[4:2], and ADDR1 is set to %1, indicating a hardware breakpoint.
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
BREAKPOINT
LOW POWER
INTERRUPT
Figure 5-12 CPU Space Address Encoding
FUNCTION
1 1 1
2
1 1 1
2
1 1 1
2
CODE
0
0
0
SYSTEM INTEGRATION MODULE
23
23
23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ADDRESS BUS
CPU SPACE
TYPE FIELD
19
19
19
CPU SPACE CYCLES
16
16
16
4
BKPT#
LEVEL
2
1
T 0
0
0
0
1
MOTOROLA
CPU SPACE CYC TIM
5-31