MC68376BGMAB20 Freescale Semiconductor, MC68376BGMAB20 Datasheet - Page 394

• Manufacturer Part Number: MC68376BGMAB20
• Description: IC MCU 32BIT 8K ROM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68376BGMAB20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Ram Size: 7.5K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

CCL — Channel Conditions Latch
BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits
D.8.4 Development Support Status Register
DSSR — Development Support Status Register
BKPT — Breakpoint Asserted Flag
PCBK — PC Breakpoint Flag
D-76
MOTOROLA
15
0
0
RESET:
CCL controls the latching of channel conditions (MRL and TDL) when the CHAN reg-
ister is written.
These bits are TPU breakpoint enables. Setting a bit enables a breakpoint condition.
Table D-55 shows the different breakpoint enable bits.
If an internal breakpoint caused the TPU to enter the halted state, the TPU asserts the
BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the TPU
recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is
asserted.
PCBK is asserted if a breakpoint occurs because of a PC (microprogram counter)
register match with the PC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
0 = Only the pin state condition of the new channel is latched as a result of the write
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result
14
0
0
Enable Bit
CHAN register microinstruction.
of a write CHAN register microinstruction.
BM
BP
BC
BH
BL
BT
13
0
0
12
Break if PC equals PC breakpoint register
Break if CHAN register equals channel breakpoint register at beginning of state or
when CHAN is changed through microcode
Break if host service latch is asserted at beginning of state
Break if link service latch is asserted at beginning of state
Break if MRL is asserted at beginning of state
Break if TDL is asserted at beginning of state
0
0
11
0
0
Table D-55 Breakpoint Enable Bits
FRZ[1:0]
00
01
10
11
10
0
0
Table D-54 FRZ[1:0] Encoding
REGISTER SUMMARY
9
0
0
8
0
0
Freeze at end of current microcycle
Freeze at next time-slot boundary
BKPT
7
0
Function
TPU Response
Ignore freeze
PCBK
Reserved
6
0
CHBK
5
0
SRBK
4
0
TPUF
3
0
USER’S MANUAL
2
0
0
MC68336/376
$YFFE06
1
0
0
0
0
0